The power layout of a CMOS image sensor can significantly affect performance such as resolution, frame rate, etc. This article discusses important considerations when designing a power solution for this application.
Internal structure of CMOS image sensor
A typical CMOS imaging system contains an active pixel color array, analog signal processing circuitry, analog-to-digital converters, and digital sections for control interface, timing, and data readout. The fill factor of an array is the percentage of the photosensitive portion relative to the total size of the sensor. A photodetector is a light-sensitive sensor that captures visible photons and converts them into electrical current (femtoamps). Resolution is used to quantify the total number of pixel arrays in a CMOS image sensor, for example, a 2-megapixel sensor array is 1600 columns and 1200 rows. However, not all pixels in the array are active (available for light detection), some of them (optically black) are used for black level and noise correction.
Several different pixel transistor designs are available, including three-transistor (3T), four-transistor (4T), and five-transistor (5T) versions. In a 4T layout, the photodiode converts the received visible photons into electrical charges. Each voltage is read one row at a time and placed into the column capacitor (C). It is then read using a decoder and multiplexer.
Frame rate is used to quantify how fast the image processing array can capture a complete image, typically 30-120 fps. Frame rate is affected by shutter speed, which controls how long the image sensor collects light. The programmable time interval, also known as the “dark period”, also affects the frame rate, which is about 75% of the read rate, when other tasks are performed after the last row has been read. Frames are read sequentially line by line; finally, the buffer stores the entire frame as a complete image.
Power Design Considerations
CMOS image sensors typically use three different supply rails, the analog supply rail (2.8 V AVDD), the interface supply rail (1.8 or 2.8 V DOVDD), and the digital supply rail (1.2 or 1.8 V DVDD). A low-dropout (LDO) regulator has a large bypass capacitor on the input pin to stabilize the power supply and help reduce voltage fluctuations, thereby improving image sensor noise performance. Power Supply Rejection Ratio (PSRR) measures the ability of an LDO to reject input voltage variations caused by power supply ripple, or block noise caused by other switching regulators. LDOs with low PSRR can cause unwanted horizontal ripple in the captured image. Before designing an LDO with a high enough PSRR for this application, the sensor line frequency required for a given frame rate can be calculated.
The feedback loop inside the LDO basically determines the PSRR of the system operating below 100 kHz. For higher frequency (above 100 kHz) applications, it still depends on passive components and PCB layout. Therefore, careful PCB design can achieve tight current loops and reduce parasitic inductances. Ordinary LDOs have lower PSRR at high frequencies. While this is not a problem for standard cameras, higher resolution (50−200 MP) and high frame rate image sensors require LDOs with PSRR higher than 90 dB at lower frequencies (up to 10 kHz), and at higher higher than 45 dB at frequency (1−3 MHz).
Frame rate (30−120 fps) and line rate (22−44 kHz) create dynamic loads that cause undershoot and overshoot on the analog supply rails. At each frame or line transition, the current drawn is similar to a step load, meaning that the LDO must be able to handle load changes in the hundreds of milliamps each time a frame and line (or between) is read. Bulk capacitors (low impedance at line and frame frequencies) can help decoupling the camera to reduce ripple caused by this load switching.
Each pixel of an image sensor has a charge saturation level (or maximum well capacitance), which is the amount of charge (measured in electrons) that the pixel can hold before reaching saturation. The dynamic range (expressed in dB) of an image sensor is the ratio of the brightest and darkest parts of an image that can be captured simultaneously. The low spectral noise density (between 10 Hz and 1 Mhz) at the output of the LDO also helps reduce the amount of noise transmitted to the CMOS image sensor, enabling pixels to achieve a greater dynamic range. Finally, the overall ripple and noise should be at least 40 dB below the sensor’s noise threshold, usually expressed in the data sheet as the signal-to-noise ratio (SNR).